The present invention generally relates to clock generators, and, more particularly, to clock signal generating circuits that filter out glitches in input signals and a method for generating glitch-free clock signals.
Clock generators are used for providing clock signals for various circuits. In some circuits, the clock signals are provided in response to enable signals. However, since the enable signals are provided from various other circuits, the enable circuits may have glitches. As is well understood, glitches can cause circuits to operate incorrectly and in some cases, even fail.
It would be advantageous to have a glitch-free clock generator and a method therefor.